Commit 6be5ac14 authored by Alessio Igor Bogani's avatar Alessio Igor Bogani
Browse files

Fix identation

parent 470b696f
This diff is collapsed.
......@@ -94,200 +94,200 @@ float sumf(float, float);
float mpy(float a, float b)
{return a*b;}
{return a*b;}
float sumf(float a, float b)
{return a+b;}
{return a+b;}
int main(void)
{
signed int Buffer[32];
signed int sum = 0, avg = 0;
unsigned int i, j, temp;
volatile unsigned int *po = &ADC0;
(void)ScaleA0;
(void)ScaleA1;
(void)ScaleA2;
(void)ScaleA3;
(void)ScaleA4;
(void)ScaleA5;
ADC0=0;ADC1=0;ADC2=0;ADC3=0;ADC4=0;ADC5=0;ADC6=0;
PRU1FirmRev = 20210415;
Debug0, Debug1, Debug2, Debug3 = 0;
//init SPI
SetSPI();
//init ADC
SetADCBB();
__delay_cycles(200000);
//fill the buffer
for(i = 0; i < 32; i++)
{
Buffer[i] = GetADC();
sum += Buffer[i];
__delay_cycles(20); // 200 vedere se non abbassare un pochino
}
i=0;
while(1)
{
//ADC syncronization with T0 T0 is resetting at 2000 (20us)
while(((HWREGH(0x48300208) > 200) && (HWREGH(0x48300208) < 1000)) || (HWREGH(0x48300208) > 1200)) {}
#ifdef benchmark1
HWREG(0x481ac194) = 0b1000000000;// gpio2_9 P8-44 // bit 1, pin p8-18 GPIO2_1 GPIO2_SETDATAOUT
#endif
//i = i%16; // 32
sum -= Buffer[i]; //substract old sample
Buffer[i] = GetADC(); //get new sample
sum += Buffer[i]; //add new sample
Debug0 = Buffer[i];
i++;
if (i>31) i=0;
// check the sign make average on 16 samples, divide by 16 (shift 4 times)
/* if(sum >= 0)
avg = (sum >> 4); // >>4
else
avg = ((sum >> 4) | 0x80000000); // >>4
*/
avg = sum >> 5;
//avg=GetADC();
// scale the output currrent
Debug1 = avg;
//OCnorm = mpy((float) avg,9.536752259018191355E-7); // divide by fffff/9.536752259018191355E-7 16samples 20bit (>>1)
//OCnorm = mpy((float) avg,7.6294527393E-6); // divide by 1ffff/7.6294527393E-6 18bit (>>3)
//OCnorm = mpy((float) avg,1.9073504518E-6); // divide by 7ffff/1.9073504518E-6 20bit (>>1)
OCnorm = mpy((float) avg,-12.3023170647082461E-6); // divided by (1ffff*1.612) // dovrebbe essere diviso per il max valore ammissibile
Debug2=OCnorm;
// even coefficients negated
// 40us execution time
// OutputCurrent = -(-ScaleA0+(ScaleA1*OCnorm)+(-ScaleA2*OCnorm*OCnorm)+(ScaleA3*OCnorm*OCnorm*OCnorm)+(-ScaleA4*OCnorm*OCnorm*OCnorm*OCnorm)+(ScaleA5*OCnorm*OCnorm*OCnorm*OCnorm*OCnorm))*20.0;
// 20us execution time
// OutputCurrent = -mpy(sumf(mpy(sumf(mpy(sumf(mpy(sumf(mpy(sumf(mpy(ScaleA5,OCnorm),ScaleA4),OCnorm),ScaleA3),OCnorm),ScaleA2),OCnorm),ScaleA1),OCnorm),ScaleA0),20.0);
// 7us execution time
//Output.Current= mpy(-20, OCnorm);
Output.Current = OCnorm;
__xout(10, 5, 0, Output);
#ifdef benchmark1
HWREG(0x481ac190) = 0b1000000000;// gpio2_9 P8_44 // GPIO2_CLEARDATAOUT
#endif
// all signs positive
//OutputCurrent = -(ScaleA0+(ScaleA1*OCnorm)+(ScaleA2*OCnorm*OCnorm)+(ScaleA3*OCnorm*OCnorm*OCnorm)+(ScaleA4*OCnorm*OCnorm*OCnorm*OCnorm)+(ScaleA5*OCnorm*OCnorm*OCnorm*OCnorm*OCnorm))*20.0;
//OutputCurrent = mpy(sumf(mpy(sumf(mpy(sumf(mpy(sumf(mpy(sumf(mpy(ScaleA5,OCnorm),ScaleA4),OCnorm),ScaleA3),OCnorm),ScaleA2),OCnorm),ScaleA1),OCnorm),ScaleA0),20.0);
//read internal ADC
temp = HWREG(0x44e0d100); // read FIFO data register (bit 19-16 tag, 11-0 adcdata)
j=((temp>>16) & 0x7);
*(po + j) = temp & 0xfff;
//Debug2=mpy(ADC3,0.01918);
//ADC6 &= 0xff0; // read only one channel for digital FF
//ff=mpy((ADC6+0.0),0.005);
}
}
{
signed int Buffer[32];
signed int sum = 0, avg = 0;
unsigned int i, j, temp;
volatile unsigned int *po = &ADC0;
(void)ScaleA0;
(void)ScaleA1;
(void)ScaleA2;
(void)ScaleA3;
(void)ScaleA4;
(void)ScaleA5;
ADC0=0;ADC1=0;ADC2=0;ADC3=0;ADC4=0;ADC5=0;ADC6=0;
PRU1FirmRev = 20210415;
Debug0, Debug1, Debug2, Debug3 = 0;
//init SPI
SetSPI();
//init ADC
SetADCBB();
__delay_cycles(200000);
//fill the buffer
for(i = 0; i < 32; i++)
{
Buffer[i] = GetADC();
sum += Buffer[i];
__delay_cycles(20); // 200 vedere se non abbassare un pochino
}
i=0;
while(1)
{
//ADC syncronization with T0 T0 is resetting at 2000 (20us)
while(((HWREGH(0x48300208) > 200) && (HWREGH(0x48300208) < 1000)) || (HWREGH(0x48300208) > 1200)) {}
#ifdef benchmark1
HWREG(0x481ac194) = 0b1000000000;// gpio2_9 P8-44 // bit 1, pin p8-18 GPIO2_1 GPIO2_SETDATAOUT
#endif
//i = i%16; // 32
sum -= Buffer[i]; //substract old sample
Buffer[i] = GetADC(); //get new sample
sum += Buffer[i]; //add new sample
Debug0 = Buffer[i];
i++;
if (i>31) i=0;
// check the sign make average on 16 samples, divide by 16 (shift 4 times)
/* if(sum >= 0)
avg = (sum >> 4); // >>4
else
avg = ((sum >> 4) | 0x80000000); // >>4
*/
avg = sum >> 5;
//avg=GetADC();
// scale the output currrent
Debug1 = avg;
//OCnorm = mpy((float) avg,9.536752259018191355E-7); // divide by fffff/9.536752259018191355E-7 16samples 20bit (>>1)
//OCnorm = mpy((float) avg,7.6294527393E-6); // divide by 1ffff/7.6294527393E-6 18bit (>>3)
//OCnorm = mpy((float) avg,1.9073504518E-6); // divide by 7ffff/1.9073504518E-6 20bit (>>1)
OCnorm = mpy((float) avg,-12.3023170647082461E-6); // divided by (1ffff*1.612) // dovrebbe essere diviso per il max valore ammissibile
Debug2=OCnorm;
// even coefficients negated
// 40us execution time
// OutputCurrent = -(-ScaleA0+(ScaleA1*OCnorm)+(-ScaleA2*OCnorm*OCnorm)+(ScaleA3*OCnorm*OCnorm*OCnorm)+(-ScaleA4*OCnorm*OCnorm*OCnorm*OCnorm)+(ScaleA5*OCnorm*OCnorm*OCnorm*OCnorm*OCnorm))*20.0;
// 20us execution time
// OutputCurrent = -mpy(sumf(mpy(sumf(mpy(sumf(mpy(sumf(mpy(sumf(mpy(ScaleA5,OCnorm),ScaleA4),OCnorm),ScaleA3),OCnorm),ScaleA2),OCnorm),ScaleA1),OCnorm),ScaleA0),20.0);
// 7us execution time
//Output.Current= mpy(-20, OCnorm);
Output.Current = OCnorm;
__xout(10, 5, 0, Output);
#ifdef benchmark1
HWREG(0x481ac190) = 0b1000000000;// gpio2_9 P8_44 // GPIO2_CLEARDATAOUT
#endif
// all signs positive
//OutputCurrent = -(ScaleA0+(ScaleA1*OCnorm)+(ScaleA2*OCnorm*OCnorm)+(ScaleA3*OCnorm*OCnorm*OCnorm)+(ScaleA4*OCnorm*OCnorm*OCnorm*OCnorm)+(ScaleA5*OCnorm*OCnorm*OCnorm*OCnorm*OCnorm))*20.0;
//OutputCurrent = mpy(sumf(mpy(sumf(mpy(sumf(mpy(sumf(mpy(sumf(mpy(ScaleA5,OCnorm),ScaleA4),OCnorm),ScaleA3),OCnorm),ScaleA2),OCnorm),ScaleA1),OCnorm),ScaleA0),20.0);
//read internal ADC
temp = HWREG(0x44e0d100); // read FIFO data register (bit 19-16 tag, 11-0 adcdata)
j=((temp>>16) & 0x7);
*(po + j) = temp & 0xfff;
//Debug2=mpy(ADC3,0.01918);
//ADC6 &= 0xff0; // read only one channel for digital FF
//ff=mpy((ADC6+0.0),0.005);
}
}
signed int GetADC()
{
// Description Analog input Digital code
// FSR − 1LSB +4.999962 V 0x1FFFF
// Midscale + 1LSB +38.15 µV 0x00001
// Midscale 0 V 0x00000
// Midscale − 1LSB −38.15 µV 0x3FFFF
//−FSR + 1LSB −4.999962 V 0x20001
//−FSR −5 V 0x20000
unsigned int retval;
HWREG(0x4804c194)=(1<<28); //set CONV pin
__delay_cycles(440); //wait 2,2 us 440
HWREG(0x4804c190)=(1<<28); //clear CONV pin
__delay_cycles(10);
retval = HWREG(0x481a013c); //read data (data from previous conversion, start readback of new data)
//convert to U2
//retval += 0x20000;
//retval &= 0x3FFFF; // now -Max=0, 0=1FFFF, +Max=3FFFF
//return retval;
// MC 09/05
retval &= 0x3FFFF;
// positive 00000-1FFFF (0 - 131071dec) 0V _ 10V all'ingresso
if(retval >= 0x20000) // negative 20000-3FFFF (131072 - 262143dec) -10V _ 0V
retval |= 0xFFFE0000; // 1111|1111|1111|1110|0|0|0|0
Debug1=retval;
return retval;
}
{
// Description Analog input Digital code
// FSR − 1LSB +4.999962 V 0x1FFFF
// Midscale + 1LSB +38.15 µV 0x00001
// Midscale 0 V 0x00000
// Midscale − 1LSB −38.15 µV 0x3FFFF
//−FSR + 1LSB −4.999962 V 0x20001
//−FSR −5 V 0x20000
unsigned int retval;
HWREG(0x4804c194)=(1<<28); //set CONV pin
__delay_cycles(440); //wait 2,2 us 440
HWREG(0x4804c190)=(1<<28); //clear CONV pin
__delay_cycles(10);
retval = HWREG(0x481a013c); //read data (data from previous conversion, start readback of new data)
//convert to U2
//retval += 0x20000;
//retval &= 0x3FFFF; // now -Max=0, 0=1FFFF, +Max=3FFFF
//return retval;
// MC 09/05
retval &= 0x3FFFF;
// positive 00000-1FFFF (0 - 131071dec) 0V _ 10V all'ingresso
if(retval >= 0x20000) // negative 20000-3FFFF (131072 - 262143dec) -10V _ 0V
retval |= 0xFFFE0000; // 1111|1111|1111|1110|0|0|0|0
Debug1=retval;
return retval;
}
void SetSPI()
{
HWREG(0x44e00050) = 0x2; //enable clock for SPI1
HWREG(0x481a0110) = 0x1; //reset spi1
while((HWREG(0x481a0114) & 0x1) == 0) {} //wait for reset
//config SPI1
HWREG(0x481a0128) = 0x1; //module configuration
//HWREG(0x481a0110) = 0x15; //system configuration
HWREG(0x481a012c) = 0x171888; //ch0 configuration
HWREG(0x481a0140) = 0x6188a; //?ch1 congiguration (read)
HWREG(0x481a0154) = 0x6188a; //?ch2 congiguration (read)
HWREG(0x481a0168) = 0x6188a; //?ch3 congiguration (read)
HWREG(0x481a0134) = 0x1; //ch0 enable
HWREG(0x481a0138) = 0x3ffff; //ch0 tx dummy
}
{
HWREG(0x44e00050) = 0x2; //enable clock for SPI1
HWREG(0x481a0110) = 0x1; //reset spi1
while((HWREG(0x481a0114) & 0x1) == 0) {} //wait for reset
//config SPI1
HWREG(0x481a0128) = 0x1; //module configuration
//HWREG(0x481a0110) = 0x15; //system configuration
HWREG(0x481a012c) = 0x171888; //ch0 configuration
HWREG(0x481a0140) = 0x6188a; //?ch1 congiguration (read)
HWREG(0x481a0154) = 0x6188a; //?ch2 congiguration (read)
HWREG(0x481a0168) = 0x6188a; //?ch3 congiguration (read)
HWREG(0x481a0134) = 0x1; //ch0 enable
HWREG(0x481a0138) = 0x3ffff; //ch0 tx dummy
}
void SetADCBB()
{
//configure steps pag 1749 spruh73l
HWREG(0x44e004bc) = 0x2; //enable clock
__delay_cycles(200000);
HWREG(0x44e0d010) = 0x8; // SYSCONFIG, smart idle mode
HWREG(0x44e0d030) = 0xfff; // IRQENABLE_CLR, disable interrupts
HWREG(0x44e0d03c) = 0x3; // DMAENABLE_CLR, disable DMA
HWREG(0x44e0d040) = 0x4; // CTRL register, enable step registers write, disable module
HWREG(0x44e0d04c) = 0x3; // ADC_CLKDIV, clock divider //0x3
HWREG(0x44e0d054) = 0xfe; // STEPENABLE reg, enable step 1..7
//configure steps pag 1773 spruh73l
HWREG(0x44e0d064) = 0x1803011; //configure step 1 //LSB 3011 for 16 averages
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch1 sw conf,Vrefn
HWREG(0x44e0d068) = 0xff00ffff; //step 1 delay
HWREG(0x44e0d06c) = 0x1883011; //configure step 2
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch2 sw conf,Vrefn
HWREG(0x44e0d070) = 0xff00ffff; //step 2 delay
HWREG(0x44e0d074) = 0x1903011; //configure step 3
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch3 sw conf,Vrefn
HWREG(0x44e0d078) = 0xff00ffff; //step 3 delay
HWREG(0x44e0d07c) = 0x1983011; //configure step 4
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch4 sw conf,Vrefn
HWREG(0x44e0d080) = 0xff00ffff; //step 4 delay
HWREG(0x44e0d084) = 0x1A03011; //configure step 5
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch5 sw conf,Vrefn
HWREG(0x44e0d088) = 0xff00ffff; //step 5 delay
HWREG(0x44e0d08c) = 0x1A83011; //configure step 6
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch6 sw conf,Vrefn
HWREG(0x44e0d090) = 0xff00ffff; //step 6 delay
HWREG(0x44e0d094) = 0x1B03011; //configure step 7
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch7 sw conf,Vrefn
HWREG(0x44e0d098) = 0xff00ffff; //step 7 delay
HWREG(0x44e0d040) = 0x3; //CTRL register, enable, keep step registers protected, store channel ID tag
}
{
//configure steps pag 1749 spruh73l
HWREG(0x44e004bc) = 0x2; //enable clock
__delay_cycles(200000);
HWREG(0x44e0d010) = 0x8; // SYSCONFIG, smart idle mode
HWREG(0x44e0d030) = 0xfff; // IRQENABLE_CLR, disable interrupts
HWREG(0x44e0d03c) = 0x3; // DMAENABLE_CLR, disable DMA
HWREG(0x44e0d040) = 0x4; // CTRL register, enable step registers write, disable module
HWREG(0x44e0d04c) = 0x3; // ADC_CLKDIV, clock divider //0x3
HWREG(0x44e0d054) = 0xfe; // STEPENABLE reg, enable step 1..7
//configure steps pag 1773 spruh73l
HWREG(0x44e0d064) = 0x1803011; //configure step 1 //LSB 3011 for 16 averages
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch1 sw conf,Vrefn
HWREG(0x44e0d068) = 0xff00ffff; //step 1 delay
HWREG(0x44e0d06c) = 0x1883011; //configure step 2
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch2 sw conf,Vrefn
HWREG(0x44e0d070) = 0xff00ffff; //step 2 delay
HWREG(0x44e0d074) = 0x1903011; //configure step 3
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch3 sw conf,Vrefn
HWREG(0x44e0d078) = 0xff00ffff; //step 3 delay
HWREG(0x44e0d07c) = 0x1983011; //configure step 4
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch4 sw conf,Vrefn
HWREG(0x44e0d080) = 0xff00ffff; //step 4 delay
HWREG(0x44e0d084) = 0x1A03011; //configure step 5
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch5 sw conf,Vrefn
HWREG(0x44e0d088) = 0xff00ffff; //step 5 delay
HWREG(0x44e0d08c) = 0x1A83011; //configure step 6
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch6 sw conf,Vrefn
HWREG(0x44e0d090) = 0xff00ffff; //step 6 delay
HWREG(0x44e0d094) = 0x1B03011; //configure step 7
// sw ena cont,16 samp avg,Vrefp,ch1 neg,ch7 sw conf,Vrefn
HWREG(0x44e0d098) = 0xff00ffff; //step 7 delay
HWREG(0x44e0d040) = 0x3; //CTRL register, enable, keep step registers protected, store channel ID tag
}
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